During the manufacturing of semiconductor devices, layers of dielectrics and metal are added onto a wafer until a final layer of metal is added, hereinafter referred to as the top metal level or layer. Over this top metal layer is typically placed a barrier, passivation or CAPS (Coat and Protective Seal) layer. This passivation layer acts to maintain the mechanical integrity of the semiconductor device, prevent mobile ion diffusion, and provide some radiation protection for the semiconductor device.
Several types of methods for applying passivation layers over a top metal layer have been used in the semiconductor industry. One such passivation level is a bi-layer in which the bottom layer is a silicon dioxide and the top layer is a silicon nitride. The silicon dioxide layer is flexible and acts as a buffer to relieve stress between the silicon nitride and the top metal layer. Thus, this bottom layer reduces the impact of the mechanisms that result in the stress void migration of the metal and also acts as a mechanical protector for the underlying structures. Although the top silicon nitride layer is more brittle, the silicon nitride layer has the advantage of being resistant to moisture and sodium penetration. Additionally, the bi-layer structure inherently eliminates the coincident occurrence of pin-hole defects.
One method of applying the silicon dioxide layer of this particular bi-layer passivation level is to use plasma enhanced chemical vapor deposition (PECVD) with tetraethlorthosilicate (TEOS) chemistry. The use of TEOS chemistry advantageously results in superior film step coverage over the patterned metal-interconnects (runners) of the top metal layer as compared to silicon nitride.
As illustrated in FIG. 1, the current methods of applying passivation layers 6 are capable of filling the gap between adjacent features 4, such as the runners, when the distance between the features is large. However, FIG. 2 illustrates a problem with current methods, including TEOS chemistry. This problem is that the gap cannot be filled as the size of features and gaps becomes smaller. These unfilled gaps subsequently become voids 8 in the passivation layer. The existence of these voids can cause reliability problems due to entrapment of gases or liquids in the voids. Also, these voids can act as stress raisers, which can result in inferior mechanical strength of the passivation layer and allow metal interconnects to stress relieve into the voids.
The inferior mechanical strength caused by the voids can be a problem when the chip is removed from the wafer and pressed into the die assembly or other chip carrier. This pressing of the chip transmits a significant force to the passivation level of the chip. A common result of such a transmission of force is damage to the runners in the top metal layer. This damage can be even more prevalent when the runners have high aspect ratios such that the height dimension is significantly greater than the width dimension. Features having this type of aspect ratio are more susceptible to a force applied in the vertical or transverse direction, which occurs when the chip is pressed. One method of compensating for the voids has been to provide a very thick passivation level. However, a thick passivation level, besides being more costly, does not solve the problems associated with the voids.
Although the previously discussed passivation layer is one type of passivation layer used in the semiconductor industry, other passivation layers are also used. Once such passivation layer is formed from polymers or other plastic-like materials. Passivation layers formed from these plastics suffer from many problems. For example, plastic contains many organic compounds which may contaminate the semiconductor device. Some of these compounds are not stable at the temperatures required for the board solder assembly process. Also, these plastic-like materials tend to absorb excessive moisture, which can also contaminate the semiconductor device and cause device degradation and interfacial damage in a package environment.
A recently introduced process to apply oxides on semiconductor devices is high density plasma chemical vapor deposition (HDP CVD). This process is described by S. V. Nguyen, "High-Density Plasma Chemical Vapor Deposition of Silicon-Based Dielectric Films for Integrated Circuits," in IBM Journal of Research & Development, Vol. 43, No. 1/2 (1998) and is incorporated by reference herein.
HDP CVD has been used to fill and locally planarize high-aspect-ratio (i.e., up to 4:1) sub-half-micron structures. Generally with HDP CVD, ions and electrons are generated by means of an rf power source. Also, a rf biasing power source is applied to an electrode holding the wafer to create a significant ion bombardment (sputter-etching) during deposition. As such, when HDP CVD is used for gap filling, this is a technique in which deposited films are sputtered off by reactive ions and radicals during deposition.
The deposition/sputtering-rate ratio (D/S) is a commonly used measure of the gap-filling capability of the process. This ratio is defined as: EQU D/S=(net deposition rate+blanket sputtering rate)/blanket sputtering rate.
In general, the use of a lower D/S ratio facilitates the filling of a structure with a higher aspect ratio, but at a lower net deposition rate.
A typical HDP CVD process uses a relatively low pressure of 2-10 mTorr to achieve a high electron density (10.sup.10 -10.sup.12 cm.sup.3) and a high fractional ionization rate (10.sup.-4 to 10.sup.-1). As a high film-deposition rate is required for most applications, the process typically uses simple initial reactant gases such as silane, silicon tetrafluoride, and oxygen. Argon is added to raise the sputter rate due to its large mass. To achieve a significant deposition rate while maintaining a reasonably high sputter-etching rate for gap-filling purposes, a significant amount of initial reactant (i.e., deposited species in the plasma) must flow through the reactor. However, the system should be kept at low pressure constantly during deposition to facilitate high sputter rates. Therefore, the vacuum system for such a system typically has a high pumping capability. Also, the pumping system is generally designed to withstand the high temperature and high reactivity of the reaction by-products while removing them at a high rate. For an HDP CVD system, an advanced turbomolecular pump is generally required to achieve a suitable gap fill rate (at low pressure) and acceptable pumping reliability
As previously stated, the use of HDP CVD of silicon oxide, particularly during high rf biasing gap-fill conditions, produces simultaneous deposition and etching. This result has been used to provide void-free gap fill during the processing of semiconductor devices. Current developments in HDP CVD are working to provide void-free gap fill of high-aspect-ratio (&gt;2:1) sub-half-micron structures. However, these techniques have generally been limited to interlevel insulation, gate conductors, and shallow-trench isolation structures and has not been used to apply a dielectric layer to a top metal layer.